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Copyright74107 - 74148 DATAcopyright

LM / CD 74LS00 series TTL IC's: 74107 / 74LS107 to 74148 / 74LS148 series

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These "LS" chips are basically low power drain CMOS versions of the TTL range.
Please note, we do not stock all the listed chips on this page, however we can
order these in,depending on "lead" times. These useful 74LSxxx building blocks
of logic IC's function on lower voltages, eg: typically from 4.5V ~ 5.6V D.C.

Email us :sales@unitechelectronics.com



    74107
  Dual negative-edge-triggered J-K flip-flops with reset. 
      +---+--+---+             +---+---+----+----*---+---+
   1J |1  +--+ 14| VCC         | J | K |/CLK|/RST| Q |/Q |
  /1Q |2       13| /1RST       +===+===+====+====*===+===+
   1Q |3   74  12| /1CLK       | X | X |  X |  0 | 0 | 1 |
   1K |4  107  11| 2K          | 0 | 0 |  \ |  1 | - | - |
   2Q |5       10| /2RST       | 0 | 1 |  \ |  1 | 0 | 1 |
  /2Q |6        9| /2CLK       | 1 | 0 |  \ |  1 | 1 | 0 |
  GND |7        8| 2J          | 1 | 1 |  \ |  1 |/Q | Q |
      +----------+             | X | X | !\ |  1 | - | - |
                               +---+---+----+----*---+---+

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    74109
  Dual J-/K flip-flops with set and reset. 
        +---+--+---+           +---+---+---+----+----*---+---+
  /1RST |1  +--+ 16| VCC       | J |/K |CLK|/SET|/RST| Q |/Q |
     1J |2       15| /2RST     +===+===+===+====+====*===+===+
    /1K |3       14| 2J        | X | X | X |  0 |  0 | 1 | 1 |
   1CLK |4   74  13| /2K       | X | X | X |  0 |  1 | 1 | 0 |
  /1SET |5  109  12| 2CLK      | X | X | X |  1 |  0 | 0 | 1 |
     1Q |6       11| /2SET     | 0 | 0 | / |  1 |  1 | 0 | 1 |
    /1Q |7       10| 2Q        | 0 | 1 | / |  1 |  1 | - | - |
    GND |8        9| /2Q       | 1 | 0 | / |  1 |  1 |/Q | Q |
        +----------+           | 1 | 1 | / |  1 |  1 | 1 | 0 |
                               | X | X |!/ |  1 |  1 | - | - |
                               +---+---+---+----+----*---+---+


    74112
  Dual negative-edge-triggered J-K flip-flops with set and reset. 
        +---+--+---+           +---+---+----+----+----*---+---+
  /1CLK |1  +--+ 16| VCC       | J | K |/CLK|/SET|/RST| Q |/Q |
     1K |2       15| /1RST     +===+===+====+====+====*===+===+
     1J |3       14| /2RST     | X | X |  X |  0 |  0 | 0 | 0 |
  /1SET |4   74  13| /2CLK     | X | X |  X |  0 |  1 | 1 | 0 |
     1Q |5  112  12| 2K        | X | X |  X |  1 |  0 | 0 | 1 |
    /1Q |6       11| 2J        | 0 | 0 |  \ |  1 |  1 | - | - |
    /2Q |7       10| /2SET     | 0 | 1 |  \ |  1 |  1 | 0 | 1 |
    GND |8        9| 2Q        | 1 | 0 |  \ |  1 |  1 | 1 | 0 |
        +----------+           | 1 | 1 |  \ |  1 |  1 |/Q | Q |
                               | X | X | !\ |  1 |  1 | - | - |
                               +---+---+----+----+----*---+---+

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    74113
  Dual negative-edge-triggered J-K flip-flop with set. 
        +---+--+---+           +---+---+----+----*---+---+
  /1CLK |1  +--+ 14| VCC       | J | K |/CLK|/SET| Q |/Q |
     1K |2       13| /2CLK     +===+===+====+====*===+===+
     1J |3  74   12| 2K        | X | X |  X |  0 | 1 | 0 |
  /1SET |4  113  11| 2J        | X | X |  X |  1 | 0 | 1 |
     1Q |5       10| /2SET     | 0 | 0 |  \ |  1 | - | - |
    /1Q |6        9| 2Q        | 0 | 1 |  \ |  1 | 0 | 1 |
    GND |7        8| /2Q       | 1 | 0 |  \ |  1 | 1 | 0 |
        +----------+           | 1 | 1 |  \ |  1 |/Q | Q |
                               | X | X | !\ |  1 | - | - |
                               +---+---+----+----*---+---+


    74114
  Dual negative-edge-triggered J-K flip-flop with set, 
  common clock and common reset. 
        +---+--+---+           +---+---+----+----+----*---+---+
   /RST |1  +--+ 14| VCC       | J | K |/CLK|/SET|/RST| Q |/Q |
     1K |2       13| /CLK      +===+===+====+====+====*===+===+
     1J |3  74   12| 2K        | X | X |  X |  0 |  0 | ? | ? |
  /1SET |4  114  11| 2J        | X | X |  X |  0 |  1 | 1 | 0 |
     1Q |5       10| /2SET     | X | X |  X |  1 |  0 | 0 | 1 |
    /1Q |6        9| 2Q        | 0 | 0 |  \ |  1 |  1 | - | - |
    GND |7        8| /2Q       | 0 | 1 |  \ |  1 |  1 | 0 | 1 |
        +----------+           | 1 | 0 |  \ |  1 |  1 | 1 | 0 |
                               | 1 | 1 |  \ |  1 |  1 |/Q | Q |
                               | X | X | !\ |  1 |  1 | - | - |
                               +---+---+----+----+----*---+---+

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    74121
  Monostable multivibrator with Schmitt-trigger inputs.
  Programmable output pulse width from 40 ns and up to 20 seconds. 
       +---+--+---+
    /Q |1  +--+ 14| VCC
       |2       13|
  /TR1 |3   74  12|
  /TR2 |4  121  11| RCext
    TR |5       10| Cext
     Q |6        9| Rint
   GND |7        8|
       +----------+


    74122
  Retriggerable monostable multivibrator with overriding 
  reset and integrated 10k timing resistor. 
       +---+--+---+
  /TR1 |1  +--+ 14| VCC
  /TR2 |2       13| RCext
   TR1 |3   74  12|
   TR2 |4  122  11| Cext
  /RST |5       10|
    /Q |6        9| Rint
   GND |7        8| Q
       +----------+

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    74123
  Dual retriggerable monostable multivibrators with overriding reset. 
         +---+--+---+
    /1TR |1  +--+ 16| VCC
     1TR |2       15| 1RCext
   /1RST |3       14| 1Cext
     /1Q |4   74  13| 1Q
      2Q |5  123  12| /2Q
   2Cext |6       11| /2RST
  2RCext |7       10| 2TR
     GND |8        9| /2TR
         +----------+


    74125
  Quad 3-state noninverting buffer with active low enables. 

    

+---+--+---+ +---+---*---+ /1OE |1 +--+ 14| VCC | A |/OE| Y | 1A |2 13| /4OE +===+===*===+ 1Y |3 74 12| 4A | 0 | 0 | 0 | /2OE |4 125 11| 4Y | 1 | 0 | 1 | 2A |5 10| /3OE | X | 1 | Z | 2Y |6 9| 3A +---+---*---+ GND |7 8| 3Y +----------+

    Positive Logic
	    _
	Y = A

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    74126
  Quad 3-state noninverting buffer with active high enables. 

    

+---+--+---+ +---+---*---+ 1OE |1 +--+ 14| VCC | A | OE| Y | 1A |2 13| 4OE +===+===*===+ 1Y |3 74 12| 4A | X | 0 | Z | 2OE |4 126 11| 4Y | 0 | 1 | 0 | 2A |5 10| 3OE | 1 | 1 | 1 | 2Y |6 9| 3A +---+---*---+ GND |7 8| 3Y +----------+

    Positive Logic
	    _
	Y = A


    74128
  2-input NOR gates/line drivers. 
      +---+--+---+             +---+---*---+           ___
  /1Y |1  +--+ 14| VCC         | A | B |/Y |      /Y = A+B
   1A |2       13| /4Y         +===+===*===+
   1B |3       12| 4B          | 0 | 0 | 1 |
  /2Y |4  7402 11| 4A          | 0 | 1 | 0 |
   2A |5       10| /3Y         | 1 | 0 | 0 |
   2B |6        9| 3B          | 1 | 1 | 0 |
  GND |7        8| 3A          +---+---*---+
      +----------+

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    74131
  1-of-8 inverting decoder/demultiplexer with address register. 
       +---+--+---+
    S0 |1  +--+ 16| VCC
    S1 |2       15| /Y0
    S2 |3       14| /Y1
   CLK |4   74  13| /Y2
  /EN2 |5  131  12| /Y3
   EN1 |6       11| /Y4
   /Y7 |7       10| /Y5
   GND |8        9| /Y6
       +----------+


    74132
  Quad 2-input NAND gates with schmitt-trigger inputs.
  0.8V typical input hysteresis at VCC=+5V. 
      +---+--+---+             +---+---*---+           __
   1A |1  +--+ 14| VCC         | A | B |/Y |      /Y = AB
   1B |2       13| 4B          +===+===*===+
  /1Y |3       12| 4A          | 0 | 0 | 1 |
   2A |4 74132 11| /4Y         | 0 | 1 | 1 |
   2B |5       10| 3B          | 1 | 0 | 1 |
  /2Y |6        9| 3A          | 1 | 1 | 0 |
  GND |7        8| /3Y         +---+---*---+
      +----------+

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    74133
  13-input NAND gate. 
      +---+--+---+                 _____________
    A |1  +--+ 16| VCC        /Y = ABCDEFGHIJKLM
    B |2       15| M
    C |3       14| L
    D |4   74  13| K
    E |5  133  12| J
    F |6       11| I
    G |7       10| H
  GND |8        9| /Y
      +----------+


    74136
  Quad 2-input open-collector XOR gates. 
      +---+--+---+             +---+---*---+                    _   _
   1A |1  +--+ 14| VCC         | A | B | Y |       Y = A$B = (A.B)+(A.B)
   1B |2       13| 4B          +===+===*===+
   1Y |3       12| 4A          | 0 | 0 | 0 |
   2A |4 74136 11| 4Y          | 0 | 1 | Z |
   2B |5       10| 3B          | 1 | 0 | Z |
   2Y |6        9| 3A          | 1 | 1 | 0 |
  GND |7        8| 3Y          +---+---*---+
      +----------+

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    74137
  1-of-8 inverting decoder/demultiplexer with address latches. 
       +---+--+---+
    S0 |1  +--+ 16| VCC
    S1 |2       15| /Y0
    S2 |3       14| /Y1
   /LE |4   74  13| /Y2
  /EN2 |5  137  12| /Y3
   EN1 |6       11| /Y4
   /Y7 |7       10| /Y5
   GND |8        9| /Y6
       +----------+


    74138
  1-of-8 inverting decoder/demultiplexer. 
       +---+--+---+            +---+----+----+---+---+---*---+---+---+---+
    S0 |1  +--+ 16| VCC        |EN1|/EN2|/EN3| S2| S1| S0|/Y0|/Y1|...|/Y7|
    S1 |2       15| /Y0        +===+====+====+===+===+===*===+===+===+===+
    S2 |3       14| /Y1        | 0 | X  |  X | X | X | X | 1 | 1 | 1 | 1 |
  /EN3 |4   74  13| /Y2        | 1 | 1  |  X | X | X | X | 1 | 1 | 1 | 1 |
  /EN2 |5  138  12| /Y3        | 1 | 0  |  1 | X | X | X | 1 | 1 | 1 | 1 |
   EN1 |6       11| /Y4        | 1 | 0  |  0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
   /Y7 |7       10| /Y5        | 1 | 0  |  0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 |
   GND |8        9| /Y6        | 1 | 0  |  0 | . | . | . | 1 | 1 | . | 1 |
       +----------+            | 1 | 0  |  0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
                               +---+----+----+---+---+---*---+---+---+---+

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    74139
  Dual 1-of-4 inverting decoder/demultiplexer. 
       +---+--+---+            +---+---+---*---+---+---+---+
  /1EN |1  +--+ 16| VCC        |/EN| S1| S0|/Y0|/Y1|/Y2|/Y3|
   1S0 |2       15| /2EN       +===+===+===*===+===+===+===+
   1S1 |3       14| 2S0        | 1 | X | X | 1 | 1 | 1 | 1 |
  /1Y0 |4   74  13| 2S1        | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
  /1Y1 |5  139  12| /2Y0       | 0 | 0 | 1 | 1 | 0 | 1 | 1 |
  /1Y2 |6       11| /2Y1       | 0 | 1 | 0 | 1 | 1 | 0 | 1 |
  /1Y3 |7       10| /2Y2       | 0 | 1 | 1 | 1 | 1 | 1 | 0 |
   GND |8        9| /2Y3       +---+---+---*---+---+---+---+
       +----------+


    74140
  Dual 4-input NAND gates/50R line drivers. 
      +---+--+---+             +---+---+---+---*---+        ____
   1A |1  +--+ 14| VCC         | A | B | C | D |/Y |   /Y = ABCD
   1B |2       13| 2D          +===+===+===+===*===+
      |3   74  12| 2C          | 0 | X | X | X | 1 |
   1C |4  140  11|             | 1 | 0 | X | X | 1 |
   1D |5       10| 2B          | 1 | 1 | 0 | X | 1 |
  /1Y |6        9| 2A          | 1 | 1 | 1 | 0 | 1 |
  GND |7        8| /2Y         | 1 | 1 | 1 | 1 | 0 |
      +----------+             +---+---+---+---*---+

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    74141
  1-of-10 inverting decoder/demultiplexer. 
      +---+--+---+             +---+---+---+---*---+---+---+---+
  /Y8 |1  +--+ 16| /Y0         | S3| S2| S1| S0|/Y0|/Y1|...|/Y9|
  /Y9 |2       15| /Y1         +===+===+===+===*===+===+===+===+
   S0 |3       14| /Y5         | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
   S3 |4   74  13| /Y4         | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 |
  VCC |5  141  12| GND         | . | . | . | . | 1 | 1 | . | 1 |
   S1 |6       11| /Y6         | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
   S2 |7       10| /Y7         | 1 | 0 | 1 | X | 1 | 1 | 1 | 1 |
  /Y2 |8        9| /Y3         | 1 | 1 | X | X | 1 | 1 | 1 | 1 |
      +----------+             +---+---+---+---*---+---+---+---+


    74145
  1-of-10 open-collector inverting decoder/demultiplexer. 
      +---+--+---+             +---+---+---+---*---+---+---+---+
  /Y0 |1  +--+ 16| VCC         | S3| S2| S1| S0|/Y0|/Y1|...|/Y9|
  /Y1 |2       15| S0          +===+===+===+===*===+===+===+===+
  /Y2 |3       14| S1          | 0 | 0 | 0 | 0 | 0 | Z | Z | Z |
  /Y3 |4   74  13| S2          | 0 | 0 | 0 | 1 | Z | 0 | Z | Z |
  /Y4 |5  145  12| S3          | . | . | . | . | Z | Z | . | Z |
  /Y5 |6       11| /Y9         | 1 | 0 | 0 | 1 | Z | Z | Z | 0 |
  /Y6 |7       10| /Y8         | 1 | 0 | 1 | X | Z | Z | Z | Z |
  GND |8        9| /Y7         | 1 | 1 | X | X | Z | Z | Z | Z |
      +----------+             +---+---+---+---*---+---+---+---+

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    74147
  10-to-4 line inverting priority encoder. 
      +---+--+---+
  /A4 |1  +--+ 16| VCC
  /A5 |2       15|
  /A6 |3       14| Y3
  /A7 |4   74  13| /A3
  /A8 |5  147  12| /A2
   Y2 |6       11| /A1
   Y1 |7       10| /A9
  GND |8        9| Y0
      +----------+


    74148
  8-to-3 line inverting priority encoder with cascade inputs. 
      +---+--+---+
  /A4 |1  +--+ 16| VCC
  /A5 |2       15| /EO
  /A6 |3       14| /GS
  /A7 |4   74  13| /A3
  /EI |5  148  12| /A2
   Y2 |6       11| /A1
   Y1 |7       10| /A0
  GND |8        9| Y0
      +----------+

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We believe the above information to be correct, however,  typographical errors 
can occur and it is for this very reason, we provide the above information "as is" 
with "no Warranty" as to "correctness" nor to its "accuracy". Please, always 
check  with your " own data books "  or via a "Google" search on the net.
Please notify us if you have discovered a typographical error and we will fix it.
 E. &. O. E.
This page was upgraded January 31st 2013